第二次

module top;

wire a,b;

wire sum,c_out;

system_clock #100 clock1(a);

system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodulemodule

Add_half(sum,c_out, a, b);

input a,b;

output sum,c_out;

wire c_out_bar;

xor(sum, a, b);

nand(c_out_bar, a, b);

not(c_out,c_out_bar);

endmodulemodule system_clock(clk);

parameter PERIOD = 100;

output clk;

reg clk;

initialclk = 0;

alwaysbegin#(PERIOD/2) clk = ~clk;

#(PERIOD/2) clk = ~clk;

end

always@(posedge clk)

if($time > 1000) #(PERIOD-1)$stop;

endmodule

First

module top;

wire a,b;

reg c;

System_clock #100 clock1(a);

System_clock #50 clock2(b);

always

#1 c=a&b;

endmodulemodule

System_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial

clk=0;

always

begin

#(PERIOD/2)clk=~clk;

#(PERIOD/2)clk=~clk;

end

always@(posedge clk)

if ($time>1000)

#(PERIOD-1)$stop;

endmodule